HD6473032F16 Datasheet, PDF (454/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 12 Watchdog Timer
12.1.2 Block Diagram
Figure 12.1 shows a block diagram of the WDT.
Overflow
Interrupt signal
Interrupt
(interval timer) ^control
TCNT
TCSR
RSTCSR
Reset (internal)
Reset control
Clock
Clock
selector
Legend:
TCNT: Timer counter
TCSR: Timer control/status register
RSTCSR: Reset control/status register
Figure 12.1 WDT Block Diagram
Read/
write
control
Internal
data bus
Internal clock sources
φ/2
φ/32
φ/64
φ/128
φ/256
φ/512
φ/2048
φ/4096
12.1.3 Register Configuration
Table 12.1 summarizes the WDT registers.
Table 12.1 WDT Registers
Address^*1
Write^*2 Read
Name
H'FFA8 H'FFA8 Timer control/status register
H'FFA9 Timer counter
H'FFAA H'FFAB Reset control/status register
Notes: 1. Lower 16 bits of the address.
2. Write word data starting at this address.
3. Only 0 can be written in bit 7, to clear the flag.
Abbre-
viation
TCSR
TCNT
RSTCSR
R/W
R/(W)^*3
R/W
R/(W)^*3
Initial
Value
H'18
H'00
H'3F
Rev. 3.00 Mar 21, 2006 page 424 of 814
REJ09B0302-0300