HD6473032F16 Datasheet, PDF (603/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 18 ROM
Bits 7 to 4—Reserved: These bits always read 1.
Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in
RAM. When RAMS = 1, all flash memory block are program/erase-protected.
Bit 3: RAMS
0
1
Description
Emulation not selected
(Initial value)
Program/erase-protection of all flash memory blocks is disabled
Emulation selected
Program/erase-protection of all flash memory blocks is enabled
Bits 2 to 0—Flash Memory Area Selection: These bits are used together with bit 3 to select the
flash memory area to be overlapped with RAM. (See table 18.4.)
Table 18.4 Flash Memory Area Divisions
Addresses
H'FFE000–H'FFEFFF
H'000000–H'000FFF
H'001000–H'001FFF
H'002000–H'002FFF
H'003000–H'003FFF
H'004000–H'004FFF
H'005000–H'005FFF
H'006000–H'006FFF
H'007000–H'007FFF
Legend:
*: Don't care
Block Name
RAM area 4 kbytes
EB0 (4 kbytes)
EB1 (4 kbytes)
EB2 (4 kbytes)
EB3 (4 kbytes)
EB4 (4 kbytes)
EB5 (4 kbytes)
EB6 (4 kbytes)
EB7 (4 kbytes)
RAMS
0
1
1
1
1
1
1
1
1
RAM1
*
0
0
0
0
1
1
1
1
RAM1
*
0
0
1
1
0
0
1
1
RAM0
*
0
1
0
1
0
1
0
1
Rev. 3.00 Mar 21, 2006 page 573 of 814
REJ09B0302-0300