HD6473032F16 Datasheet, PDF (232/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 8 DMA Controller
Bit 7—Data Transfer Enable (DTE): Together with the DTME bit in DTCRB, this bit enables
or disables data transfer on the channel. When the DTME and DTE bits are both set to 1, the
channel is enabled. If auto-request is specified, data transfer begins immediately. Otherwise, the
channel waits for transfers to be requested. When the specified number of transfers have been
completed, the DTE bit is automatically cleared to 0. When DTE is 0, the channel is disabled and
does not accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then
writing 1.
Bit 7: DTE
0
1
Description
Data transfer is disabled (DTE is cleared to 0 when the specified number of
transfers have been completed)
(Initial value)
Data transfer is enabled
If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0.
Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer.
Bit 6: DTSZ
0
1
Description
Byte-size transfer
Word-size transfer
(Initial value)
Bit 5—Source Address Increment/Decrement (SAID) and Bit 4—Source Address
Increment/Decrement Enable (SAIDE): These bits select whether the source address register
(MARA) is incremented, decremented, or held fixed during the data transfer.
Bit 5: SAID
0
1
Bit 4: SAIDE Description
0
MARA is held fixed
(Initial value)
1
MARA is incremented after each data transfer
• If DTSZ = 0, MARA is incremented by 1 after each transfer
• If DTSZ = 1, MARA is incremented by 2 after each transfer
0
MARA is held fixed
1
MARA is decremented after each data transfer
• If DTSZ = 0, MARA is decremented by 1 after each transfer
• If DTSZ = 1, MARA is decremented by 2 after each transfer
Rev. 3.00 Mar 21, 2006 page 202 of 814
REJ09B0302-0300