HD6473032F16 Datasheet, PDF (418/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between Counter Clearing by Input Capture and Counter Increment: If an input
capture signal and counter increment signal occur simultaneously, the counter is cleared according
to the input capture signal. The counter is not incremented by the increment signal. The value
before the counter is cleared is transferred to the general register. See figure 10.67.
φ
Input capture signal
Counter clear signal
TCNT input clock
TCNT
N
H'0000
GR
N
Figure 10.67 Contention between Counter Clearing by Input Capture and Counter
Increment
Rev. 3.00 Mar 21, 2006 page 388 of 814
REJ09B0302-0300