HD6473032F16 Datasheet, PDF (488/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 13 Serial Communication Interface
The BRR setting is calculated as follows:
Asynchronous mode:
φ
N=
64 × 2^2n–1 × B
× 10⁶ – 1
Synchronous mode:
φ
N=
8 × 2^2n–1 × B
× 10⁶ – 1
B: Bit rate (bits/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: System clock frequency (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3)
(For the clock sources and values of n, see the following table.)
SMR Settings
n
Clock Source
CKS1
CKS0
0
φ
0
0
1
φ/4
0
1
2
φ/16
1
0
3
φ/64
1
1
The bit rate error in asynchronous mode is calculated as follows.
Error (%) =
φ × 10⁶
(N + 1) × B × 64 × 2^{2n–1 – 1 × 100}
Rev. 3.00 Mar 21, 2006 page 458 of 814
REJ09B0302-0300