HD6473032F16 Datasheet, PDF (619/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 18 ROM
18.7.4 Erase Mode
To erase an individual flash memory block, follow the erase/erase-verify flowchart (single-block
erase) shown in figure 18.13.
The wait times after bits are set or cleared in the flash memory control register (FLMCR1,
FLMCR2) and the maximum number of erase operations (N) are shown in table 21.10 in section
21.2.5, Flash Memory Characteristics.
To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in
erase block register 1 and 2 (EBR1, EBR2) at least (tsswe) µs after setting the SWE1 and SWE2
bits to 1 in FLMCR1 and FLMCR2. Next, the watchdog timer (WDT) is set to prevent
overerasing due to program runaway, etc. Set a value greater than (tse) ms + (tsesu + tce + tcesu)
µs as the WDT overflow period. Preparation for entering erase mode (erase setup) is performed
next by setting the ESU1 and ESU2 bits in FLMCR1 and FLMCR2. The operating mode is then
switched to erase mode by setting the E1 and E2 bits in FLMCR1 and FLMCR2 after the elapse of
at least (tsesu) µs. The time during which the E1 and E2 bits are set is the flash memory erase
time. Ensure that the erase time does not exceed (tse) ms.
Note: With flash memory erasing, preprogramming (setting all memory data in the memory to
be erased to all 0) is not necessary before starting the erase procedure.
18.7.5 Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the fixed erase time, clear the E1 and E2 bits in FLMCR1 and FLMCR2, then
wait for at least (tce) µs before clearing the ESU1 and ESU2 bits to exit erase mode. After exiting
erase mode, the watchdog timer setting is also cleared. The operating mode is then switched to
erase-verify mode by setting the EV1 and EV2 bits in FLMCR1 and FLMCR2. Before reading in
erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The
dummy write should be executed after the elapse of (tsev) µs or more. When the flash memory is
read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at
least (tsevr) µs after the dummy write before performing this read operation. If the read data has
been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed.
If the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as
before. The maximum value for repetition of the erase/erase-verify sequence is indicated by the
maximum erase count (N). When verification is completed, exit erase-verify mode, and wait for at
least (tcev) µs. If erasure has been completed on all the erase blocks, clear bits SWE1 and SWE2
in FLMCR1 and FLMCR2, and leave a wait time of at least (tcswe) µs.
Rev. 3.00 Mar 21, 2006 page 589 of 814
REJ09B0302-0300