HD6473032F16 Datasheet, PDF (655/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 20 Power-Down State
20.4.3 Selection of Waiting Time for Exit from Software Standby Mode
Bits STS2 to STS0 in SYSCR and bits DIV1 and DIV0 in DIVCR should be set as follows.
Crystal Resonator: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time (for the clock to
stabilize) is at least 7 ms. Table 20.3 indicates the waiting times that are selected by STS2 to
STS0, DIV1, and DIV0 settings at various system clock frequencies.
External Clock: Set STS2 to STS0, DIV0, and DIV1 so that the waiting time is at least 100 µs.
Table 20.3 Clock Frequency and Waiting Time for Clock to Settle
Waiting
DIV1 DIV0 STS2 STS1 STS0 Time 18 MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz 1 MHz Unit
0
0
0
0
0
8192 0.46 0.51 0.65 0.8
1.0 1.3 2.0 4.1 8.2 ms
states
0
0
1
16384 0.91 1.0
1.3
1.6
2.0 2.7 4.1 8.2 16.4
states
0
1
0
32768 1.8
2.0
2.7
3.3
4.1 5.5 8.2 16.4 32.8
states
0
1
1
65536 3.6
4.1
5.5
6.6
8.2 10.9 16.4 32.8 65.5
states
1
0
0
131072 7.3
8.2
10.9 13.1 16.4 21.8 32.8 65.5 131.1
states
1
0
1
1024
0.057 0.064 0.085 0.10 0.13 0.17 0.26 0.51 1.0
states
1
1
— Illegal
setting
0
100
0 8192 0.91 1.02 1.4
1.6
2.0 2.7 4.1 8.2 16.4 ms
states
0
0
1
16384 1.8
2.0
2.7
3.3
4.1 5.5 8.2 16.4 32.8
states
0
1
0
32768 3.6
4.1
5.5
6.6
8.2 10.9 16.4 32.8 65.5
states
0
1
1
65536 7.3
8.2
10.9 13.1 16.4 21.8 32.8 65.5 131.1
states
1
0
0
131072 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 262.1
states
1
0
1
1024
0.11 0.13 0.17 0.20 0.26 0.34 0.51 1.0 2.0
states
1
1
— Illegal
setting
Rev. 3.00 Mar 21, 2006 page 625 of 814
REJ09B0302-0300