HD6473032F16 Datasheet, PDF (510/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 13 Serial Communication Interface
13.3.4 Synchronous Operation
In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses.
This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver share the same clock but are otherwise independent, so full
duplex communication is possible. The transmitter and receiver are also double buffered, so
continuous transmitting or receiving is possible by reading or writing data while transmitting or
receiving is in progress.
Figure 13.14 shows the general format in synchronous serial communication.
*
Serial clock
Serial data
One unit (character or frame) of serial data
*
LSB
Bit 0
Bit 1 Bit 2 Bit 3 Bit 4
MSB
Bit 5 Bit 6 Bit 7
Don’t care
Don’t care
Note: * High except in continuous transmitting or receiving
Figure 13.14 Data Format in Synchronous Communication
In synchronous serial communication, each data bit is placed on the communication line from one
falling edge of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock.
In each character, the serial data bits are transmitted in order from LSB (first) to MSB (last). After
output of the MSB, the communication line remains in the state of the MSB. In synchronous mode
the SCI receives data by synchronizing with the rise of the serial clock.
Communication Format: The data length is fixed at 8 bits. No parity bit or multiprocessor bit
can be added.
Clock: An internal clock generated by the on-chip baud rate generator or an external serial clock
input from the SCK pin can be selected by means of the C/A bit in SMR and bits CKE1 and CKE0
in SCR. See table 13.9 for details of SCI clock source selection.
When the SCI operates on an internal clock, the serial clock is output from the SCK pin.
Eight serial clock pulses are output per transmitted or received character. When the SCI is not
transmitting or receiving, the clock signal remains in the high state. However, in a receive-only
Rev. 3.00 Mar 21, 2006 page 480 of 814
REJ09B0302-0300