HD6473032F16 Datasheet, PDF (367/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

10.3 CPU Interface
Section 10 16-Bit Integrated Timer Unit (ITU)
10.3.1 16-Bit Accessible Registers
The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers A
and B (BRAs and BRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data
bus. These registers can be written or read a word at a time, or a byte at a time.
Figures 10.6 and 10.7 show examples of word access to a timer counter (TCNT). Figures 10.8,
10.9, 10.10, and 10.11 show examples of byte access to TCNTH and TCNTL.
On-chip data bus
H
CPU L
Bus interface
H
L
Module
data bus
TCNTH TCNTL
Figure 10.6 Access to Timer Counter (CPU Writes to TCNT, Word)
On-chip data bus
H
CPU L
Bus interface
H
L
Module
data bus
TCNTH TCNTL
Figure 10.7 Access to Timer Counter (CPU Reads TCNT, Word)
Rev. 3.00 Mar 21, 2006 page 337 of 814
REJ09B0302-0300