HD6473032F16 Datasheet, PDF(130/847 Page) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

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HD6473032F16 Datasheet, PDF (130/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

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Section 5 Interrupt Controller

a. All interrupts are

enabled

I â0

I â 1, UI â 0

b. Only NMI, IRQ2, and

IRQ3 are enabled

I â0

Exception handling,

or I â1, UI â 1

UI â 0

Exception handling,

or UI â 1

c. All interrupts are

disabled except NMI

Figure 5.5 Interrupt Enable/Disable State Transitions (Example)

Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0.

1. If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an

interrupt request is sent to the interrupt controller.

2. When the interrupt controller receives one or more interrupt requests, it selects the highest-

priority request, following the IPR interrupt priority settings, and holds other requests pending.

If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt

controller follows the priority order shown in table 5.3.

3. The interrupt controller checks the I bit. If the I bit is cleared to 0, the interrupt request is

accepted regardless of its IPR setting. The value of the UI bit is immaterial. If the I bit is set

to 1 and the UI bit is cleared to 0, only interrupt requests with priority level 1 are accepted;

interrupt requests with priority level 0 are held pending. If the I bit and UI bit are both set to 1,

the interrupt request is held pending.

4. When an interrupt request is accepted, interrupt exception handling starts after execution of the

current instruction has been completed.

5. In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is

saved indicates the address of the first instruction that will be executed after the return from the

interrupt service routine.

6. The I and UI bits are set to 1 in CCR, masking all interrupts except NMI.

7. The vector address of the accepted interrupt is generated, and the interrupt service routine

starts executing from the address indicated by the contents of the vector address.

Rev. 3.00 Mar 21, 2006 page 100 of 814

REJ09B0302-0300

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