HD6473032F16 Datasheet, PDF (415/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between General Register Write and Compare Match: If a compare match occurs
in the T₃ state of a general register write cycle, writing takes priority and the compare match signal
is inhibited. See figure 10.64.
General register write cycle
T₁
T₂
T₃
φ
Address bus
GR address
Internal write signal
TCNT
N
N+1
GR
Compare match signal
N
M
General register write data
Inhibited
Figure 10.64 Contention between General Register Write and Compare Match
Rev. 3.00 Mar 21, 2006 page 385 of 814
REJ09B0302-0300