HD6473032F16 Datasheet, PDF (431/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

11.2 Register Descriptions
Section 11 Programmable Timing Pattern Controller
11.2.1 Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register that selects input or output for each pin in port A.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
PA₇ DDR PA₆ DDR PA₅ DDR PA₄ DDR PA₃ DDR PA₂ DDR PA₁ DDR PA₀ DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port A data direction 7 to 0
These bits select input or
output for port A pins
Port A is multiplexed with pins TP₇ to TP₀. Bits corresponding to pins used for TPC output must
be set to 1. For further information about PADDR, see section 9.11, Port A.
11.2.2 Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when
these TPC output groups are used.
Bit
Initial value
Read/Write
7
PA ₇
0
R/(W)*
6
PA ₆
0
R/(W)*
5
PA ₅
0
R/(W)*
4
PA ₄
0
R/(W)*
3
PA ₃
0
R/(W)*
2
PA ₂
0
R/(W)*
1
PA ₁
0
R/(W)*
0
PA ₀
0
R/(W)*
Port A data 7 to 0
These bits store output data
for TPC output groups 0 and 1
Note: * Bits selected for TPC output by NDERA settings become read-only bits.
For further information about PADR, see section 9.11, Port A.
Rev. 3.00 Mar 21, 2006 page 401 of 814
REJ09B0302-0300