HD6473032F16 Datasheet, PDF (82/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 2 CPU
2.8.2 Program Execution State
In this state the CPU executes program instructions in normal sequence.
2.8.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from
the exception vector table and branches to that address. In interrupt and trap exception handling
the CPU references the stack pointer (ER7) and saves the program counter and condition code
register.
Types of Exception Handling and Their Priority: Exception handling is performed for resets,
interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their
priority. Trap instruction exceptions are accepted at all times in the program execution state.
Table 2.14 Exception Handling Types and Priority
Type of
Priority Exception
Detection Timing
Start of Exception Handling
High
↑





Low
Reset
Interrupt
Trap instruction
Synchronized with clock
End of instruction
execution or end of
exception handling^*
When TRAPA instruction
is executed
Exception handling starts immediately
when RES changes from low to high
When an interrupt is requested,
exception handling starts at the end of
the current instruction or current
exception-handling sequence
Exception handling starts when a trap
(TRAPA) instruction is executed
Note: * Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or
immediately after reset exception handling.
Figure 2.11 classifies the exception sources. For further details about exception sources, vector
numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt
Controller.
Rev. 3.00 Mar 21, 2006 page 52 of 814
REJ09B0302-0300