HD6473032F16 Datasheet, PDF (258/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 8 DMA Controller
Figure 8.14 shows the timing when the DMAC is activated by low input at a DREQ pin. This
example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state
access area. The DMAC continues the transfer while the DREQ pin is held low.
CPU cycle
DMAC cycle
CPU cycle
DMAC cycle
(last transfer cycle)
CPU cycle
T₁ T₂ T₃ T_d T₁ T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂
φ
DREQ
Address
bus
RD
HWR , LWR
TEND
Source Destination
address address
Source Destination
address address
Figure 8.14 Bus Timing of DMA Transfer Requested by Low DREQ Input
Rev. 3.00 Mar 21, 2006 page 228 of 814
REJ09B0302-0300