HD6473032F16 Datasheet, PDF (774/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Appendix B Internal I/O Register
 Address H'FFA7
Bit
7
6
5
—
—
—
Initial value
1
1
1
Read/Write
—
—
—
TCSR—Timer Control/Status Register
Bit
Initial value
Read/Write
7
OVF
0
R/(W)*
6
WT/ IT
0
R/W
5
TME
0
R/W
4
3
2
1
0
— NDR3 NDR2 NDR1 NDR0
1
0
0
0
0
—
R/W R/W R/W R/W
Store the next output data for
TPC output group 0
H'A8
WDT
4
3
2
1
0
—
—
CKS2 CKS1 CKS0
1
1
0
0
0
—
—
R/W R/W R/W
Timer enable
0 Timer disabled
• TCNT is initialized to H'00 and halted
1 Timer enabled
• TCNT is counting
• CPU interrupt requests are enabled
Timer mode select
0 Interval timer: requests interval timer interrupts
1 Watchdog timer: generates a reset signal
Overflow flag
0 [Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
1 [Setting condition]
TCNT changes from H'FF to H'00
Note: * Only 0 can be written, to clear the flag.
Clock select 2 to 0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
φ/2
φ/32
φ/64
φ/128
φ/256
φ/512
φ/2048
φ/4096
Rev. 3.00 Mar 21, 2006 page 744 of 814
REJ09B0302-0300