HD6473032F16 Datasheet, PDF (336/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
10.1.2 Block Diagrams
ITU Block Diagram (Overall): Figure 10.1 is a block diagram of the ITU.
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
TOCXA₄, TOCXB₄
TIOCA₀ to TIOCA₄
TIOCB₀ to TIOCB₄
Clock selector
Control logic
IMIA0 to IMIA4
IMIB0 to IMIB4
OVI0 to OVI4
TOER
TOCR
TSTR
TSNC
TMDR
TFCR
Module data bus
Legend:
TOER: Timer output master enable register (8 bits)
TOCR: Timer output control register (8 bits)
TSTR: Timer start register (8 bits)
TSNC: Timer synchro register (8 bits)
TMDR: Timer mode register (8 bits)
TFCR: Timer function control register (8 bits)
Figure 10.1 ITU Block Diagram (Overall)
Rev. 3.00 Mar 21, 2006 page 306 of 814
REJ09B0302-0300