HD6473032F16 Datasheet, PDF (403/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
Figure 10.51 shows an example in which GRA is set to function as an input capture register
buffered by BRA, and TCNT is cleared by input capture B. The falling edge is selected as the
input capture edge at TIOCB. Both edges are selected as input capture edges at TIOCA. Because
of the buffer setting, when the TCNT value is captured into GRA at input capture A, the previous
GRA value is simultaneously transferred to BRA. Figure 10.52 shows the transfer timing.
TCNT value
H'0180
H'0160
Counter cleared by
input capture B
H'0005
H'0000
TIOCB
TIOCA
GRA
BRA
GRB
H'0005
Time
H'0160
H'0005
H'0160
H'0180
Input capture A
Figure 10.51 Register Buffering (Example 2: Buffering of Input Capture Register)
Rev. 3.00 Mar 21, 2006 page 373 of 814
REJ09B0302-0300