HD6473032F16 Datasheet, PDF (584/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 17 RAM
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized at the rising edge of the input at the RES pin. It is not initialized in software standby
mode.
Bit 0: RAME
0
1
Description
On-chip RAM is disabled
On-chip RAM is enabled
(Initial value)
17.3 Operation
When the RAME bit is set to 1, the on-chip RAM is enabled. Accesses to addresses H'FDF10 to
H'FFF0F in the H8/3052BF in modes 1, 2, 5, and 7, addresses H'FFDF10 to H'FFFF0F in the
H8/3052BF in modes 3, 4, and 6 are directed to the on-chip RAM. In modes 1 to 6 (expanded
modes), when the RAME bit is cleared to 0, the external address space is accessed. In mode 7
(single-chip mode), when the RAME bit is cleared to 0, the on-chip RAM is not accessed: read
access always results in H'FF data, and write access is ignored.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written
and read by word access. It can also be written and read by byte access. Byte data is accessed in
two states using the upper 8 bits of the data bus. Word data starting at an even address is accessed
in two states using all 16 bits of the data bus.
Rev. 3.00 Mar 21, 2006 page 554 of 814
REJ09B0302-0300