HD6473032F16 Datasheet, PDF (837/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
Appendix E Timing of Transition to and Recovery from
Hardware Standby Mode
E.1 Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10
system clock cycles before the STBY signal goes low, as shown below. The minimum delay
from the fall of the STBY signal to the rise of the RES signal is 0 ns.
STBY
RES
t₁ ≥ 10t_cyc
t₂ ≥ 0 ns
Figure E.1 Timing of Recovery from Hardware Standby Mode (1)
(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents
do not need to be retained, RES does not have to be driven low as in (1).
E.2 Timing of Recovery from Hardware Standby Mode
Drive the RES signal low approximately 100 ns before STBY goes high.
STBY
RES
t ≥ 100 ns
t_OSC
Figure E.2 Timing of Recovery from Hardware Standby Mode (2)
Rev. 3.00 Mar 21, 2006 page 807 of 814
REJ09B0302-0300