HD6473032F16 Datasheet, PDF (55/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 2 CPU
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the
stack.
SP (ER7)
Free area
Stack area
Figure 2.5 Stack
2.4.3 Control Registers
The control registers are the 24-bit program counter (PC) and the 8-bit condition code register
(CCR).
Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU
will execute. The length of all CPU instructions is 2 bytes (one word) or a multiple of 2 bytes, so
the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is
regarded as 0.
Condition Code Register (CCR): This 8-bit register contains internal CPU status information,
including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and
carry (C) flags.
• Bit 7—Interrupt Mask Bit (I)
Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting.
The I bit is set to 1 at the start of an exception-handling sequence.
• Bit 6—User Bit or Interrupt Mask Bit (UI)
Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC
instructions. This bit can also be used as an interrupt mask bit. For details see section 5,
Interrupt Controller.
• Bit 5—Half-Carry Flag (H)
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed,
this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the
ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a
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