HD6473032F16 Datasheet, PDF (399/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
10.4.8 Buffering
Buffering operates differently depending on whether a general register is an output compare
register or an input capture register, with further differences in reset-synchronized PWM mode and
complementary PWM mode. Buffering is available only in channels 3 and 4. Buffering operations
under the conditions mentioned above are described next.
• General register used for output compare
The buffer register value is transferred to the general register at compare match.
See figure 10.46.
Compare match signal
BR
GR
Comparator
TCNT
Figure 10.46 Compare Match Buffering
• General register used for input capture
The TCNT value is transferred to the general register at input capture. The previous general
register value is transferred to the buffer register.
See figure 10.47.
Input capture signal
BR
GR
Figure 10.47 Input Capture Buffering
TCNT
Rev. 3.00 Mar 21, 2006 page 369 of 814
REJ09B0302-0300