HD6473032F16 Datasheet, PDF (625/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Figure 18.14 shows the flash memory state transition diagram.
Section 18 ROM
P = 1 or
E=1
Memory read
verify mode
RD VF PR ER FLER = 0
P = 0 and
E=0
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Program mode
Erase mode
Reset or hardware standby
Reset or standby
(hardware protection)
RD VF PR ER FLER = 0
Error
occurrence
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RD VF PR ER INIT FLER = 0
Reset or hardware
standby
Error protection mode
RD VF PR ER FLER = 1
Software standby mode
Error protection mode
(software standby)
Software standby
mode release
RD VF PR ER INIT FLER = 1
Legend:
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
RD: Memory read not possible
VF: Verify-read not possible
PR: Programming not possible
ER: Erasing not possible
INIT: Register initialization state
Figure 18.14 Flash Memory State Transitions (Modes 5, 6, and 7
(On-Chip ROM Enabled), High Level Applied to FWE Pin)
18.8.4 NMI Input Disable Conditions
While flash memory is being programed/erased and the boot program is executing in the boot
mode (however, period up to branching to on-chip RAM area)*¹, NMI input is disabled because
the programming/erasing operations have priority.
Rev. 3.00 Mar 21, 2006 page 595 of 814
REJ09B0302-0300