HD6473032F16 Datasheet, PDF (364/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
Bit 2—Overflow Flag (OVF): This status flag indicates TCNT overflow or underflow.
Bit 2: OVF
Description
0
[Clearing condition]
(Initial value)
Read OVF when OVF = 1, then write 0 in OVF
1
[Setting condition]
TCNT overflowed from H'FFFF to H'0000, or underflowed from H'0000 to
H'FFFF^*
Notes: * TCNT underflow occurs when TCNT operates as an up/down-counter. Underflow
occurs only under the following conditions:
1. Channel 2 operates in phase counting mode (MDF = 1 in TMDR)
2. Channels 3 and 4 operate in complementary PWM mode (CMD1 = 1 and CMD0 = 0 in
TFCR)
Bit 1—Input Capture/Compare Match Flag B (IMFB): This status flag indicates GRB
compare match or input capture events.
Bit 1: IMFB
0
1
Description
[Clearing condition]
(Initial value)
Read IMFB when IMFB = 1, then write 0 in IMFB
[Setting conditions]
• TCNT = GRB when GRB functions as an output compare register.
• TCNT value is transferred to GRB by an input capture signal, when GRB
functions as an input capture register.
Bit 0—Input Capture/Compare Match Flag A (IMFA): This status flag indicates GRA
compare match or input capture events.
Bit 0: IMFA
0
1
Description
[Clearing condition]
(Initial value)
Read IMFA when IMFA = 1, then write 0 in IMFA.
DMAC activated by IMIA interrupt (channels 0 to 3 only).
[Setting conditions]
• TCNT = GRA when GRA functions as an output compare register.
• TCNT value is transferred to GRA by an input capture signal, when GRA
functions as an input capture register.
Rev. 3.00 Mar 21, 2006 page 334 of 814
REJ09B0302-0300