SH7147 Datasheet, PDF (978/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 24 List of Registers
24.1 Register Address Table (In the Order of Addresses)
Access sizes are indicated as the number of bits. Access cycles are the number of cycles of the
indicated reference clock, and the values are shown for 8-bit access (B), 16-bit access (W), or 32-
bit access (L).
Notes: 1. Access to undefined locations or reserved addresses is prohibited. Correct operation
cannot be guaranteed if such addresses are accessed.
2. Access to mailbox areas of the RCAN-ET may include wait cycles of 0 to 5 Pφ cycles.
Register Name
Abbreviation No. of Bits Address
Module
Access No. of Access
Size
Cycles
Connected
Bus Width
Serial mode register_0
SCSMR_0 8
H'FFFFC000 SCI
8
Pφ (reference clock) 16 bits
Bit rate register_0
SCBRR_0 8
H'FFFFC002 (Channel 0) 8
B: 2
Serial control register_0
SCSCR_0 8
H'FFFFC004
8
Transmit data register_0
SCTDR_0 8
H'FFFFC006
8
Serial status register_0
SCSSR_0 8
H'FFFFC008
8
Receive data register_0
SCRDR_0 8
H'FFFFC00A
8
Serial direction control register_0
SCSDCR_0 8
H'FFFFC00C
8
Serial port register_0
SCSPTR_0 8
H'FFFFC00E
8
Serial mode register_1
SCSMR_1 8
H'FFFFC080 SCI
8
Pφ (reference clock) 16 bits
Bit rate register_1
SCBRR_1 8
H'FFFFC082 (Channel 1) 8
B: 2
Serial control register_1
SCSCR_1 8
H'FFFFC084
8
Transmit data register_1
SCTDR_1 8
H'FFFFC086
8
Serial status register_1
SCSSR_1 8
H'FFFFC088
8
Receive data register_1
SCRDR_1 8
H'FFFFC08A
8
Serial direction control register_1
SCSDCR_1 8
H'FFFFC08C
8
Serial port register_1
SCSPTR_1 8
H'FFFFC08E
8
Serial mode register_2
SCSMR_2 8
H'FFFFC100 SCI
8
Pφ (reference clock) 16 bits
Bit rate register_2
SCBRR_2 8
H'FFFFC102 ^{(Channel 2)} 8
B: 2
Serial control register_2
SCSCR_2 8
H'FFFFC104
8
Transmit data register_2
SCTDR_2 8
H'FFFFC106
8
Serial status register_2
SCSSR_2 8
H'FFFFC108
8
Receive data register_2
SCRDR_2 8
H'FFFFC10A
8
Rev. 3.00 Oct. 06, 2008 Page 954 of 1080
REJ09B0230-0300