SH7147 Datasheet, PDF (735/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 Controller Area Network (RCAN-ET)
Bit[15:1]:TXCR0
0
1
Description
Transmit message cancellation idle state in corresponding mailbox (Initial
value)
[Clearing Condition] Completion of transmit message cancellation
(automatically cleared)
Transmission cancellation request made for corresponding mailbox
Bit 0 — This bit is always ‘0’ as this is a receive-only mailbox. Writing a '1' to this bit position
has no effect and always read back as a ‘0’.
(3) Transmit Acknowledge Register (TXACK0)
The TXACK0 is a 16-bit read / conditionally-write registers. This register is used to signal to the
CPU that a mailbox transmission has been successfully made. When a transmission has succeeded
the RCAN-ET sets the corresponding bit in the TXACK register. The CPU may clear a TXACK
bit by writing a '1' to the corresponding bit location. Writing a '0' has no effect.
• TXACK0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TXACK0[15:1]
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* -
Note : * Only when writing a ‘1’ to clear.
Bit 15 to 1 — notifies that the requested transmission of the corresponding Mailbox has been
finished successfully. The bit 15 to 1 corresponds to Mailbox-15 to 1 respectively.
Bit[15:1]:TXACK0 Description
0
[Clearing Condition] Writing ‘1’ (Initial value)
1
Corresponding Mailbox has successfully transmitted message (Data or
Remote Frame)
[Setting Condition] Completion of message transmission for corresponding
mailbox
Bit 0 — This bit is always ‘0’ as this is a receive-only mailbox. Writing a '1' to this bit position
has no effect and always read back as a ‘0’.
Rev. 3.00 Oct. 06, 2008 Page 711 of 1080
REJ09B0230-0300