SH7147 Datasheet, PDF (955/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Bit
10, 9
7, 6
Section 23 Advanced User Debugger (AUD)
Bit Name
OC[1:0]
WA[1:0]
Initial
Value
00
00
R/W Description
R/W Output Counter Mode
When trace data is output by a branch trace, only the
lower bits corresponding to an address change are
usually output. However, the entire 32-bit data is
periodically output and OC specifies this period. When
the OC bits in AUCSR are B'11, the changed part of an
address is always output as AUDATA trace address
output, except for the first cycle after a reset. When the
OC bits in AUCSR are B'00, a 32-bit address is output
every time128 trace data are output.
00: An entire address is output every time128 trace
data are output.
01: Reserved
10: Reserved
11: Always outputs the lower part of a changed
address
R/W Window A Data Trace Function
Setting these bits enables AUD to trace memory
access in the area designated by window A. Read
access, write access, or both can be designated as
tracing conditions. WE also designates whether the I
bus or the L bus should be traced. For details, see
section 23.3.7, AUD Extended Control Register
(AUECSR).
00: Disables window A data trace function
01: Traces only write access
10: Traces only read access
11: Traces both read and write accesses
Rev. 3.00 Oct. 06, 2008 Page 931 of 1080
REJ09B0230-0300