SH7147 Datasheet, PDF (932/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 22 Power-Down Modes
Table 22.1 States of Power-Down Modes
State
Mode
CPU
On-Chip
Transition Method CPG CPU Register Memory
On-Chip
Peripheral
Modules Canceling Procedure
Sleep
Execute SLEEP
Runs Halts Held
instruction with STBY
bit in STBCR1
cleared to 0.
Runs
Run
• Reset
Software
standby
Execute SLEEP
instruction with STBY
bit in STBCR1 and
STBYMD bit in
STBCR6 set to 1.
Halts
Halts
Held
Halts
Halt
(contents
retained)
• Interrupt by NMI or
IRQ
• Power-on reset by
the RES pin
Deep Execute SLEEP
Halts Halts Undefined Halts
Halt
software instruction with STBY
(contents
standby bit in STBCR1 set to
undefined)
1 and STBYMD bit in
STBCR6 cleared to 0.
• Power-on reset by
the RES pin
Module
standby
Set MSTP bits in
Runs Runs Held
STBCR2 to STBCR5
to 1.
Specified Specified • Clear MSTP bit to 0
module halts module
(contents halts
retained)
• Power-on reset (for
modules whose
MSTP bit has an
initial value of 0)
Hardware Drive the HSTBY pin Halts Halts Undefined Halts
Halt
standby low
(contents
undefined)
• Power-on reset by
the RES pin
Note: For details on the states of on-chip peripheral module registers in each mode, refer to
section 24.3, Register States in Each Operating Mode. For details on the pin states in each
mode, refer to appendix A, Pin States.
Rev. 3.00 Oct. 06, 2008 Page 908 of 1080
REJ09B0230-0300