SH7147 Datasheet, PDF (219/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Data Transfer Controller (DTC)
8.8 Interrupt Sources
An interrupt request is issued to the CPU when the DTC finishes the specified number of data
transfers, or on completion of a single data transfer or a single block data transfer with the DISEL
bit set to 1. In the case of interrupt activation, the interrupt set as the activation source is
generated. These interrupts to the CPU are subject to CPU mask level and priority level control in
the interrupt controller. For details, refer to section 6.8, Data Transfer with Interrupt Request
Signals.
Rev. 3.00 Oct. 06, 2008 Page 195 of 1080
REJ09B0230-0300