SH7147 Datasheet, PDF (253/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
The sequence for reclaiming the bus mastership from an external device is described below.
At 1.5 cycles after the negation of BREQ is detected at the falling edge of CK, the bus control
signals are driven high. The bus acknowledge signal is negated at the next falling edge of the
clock. The fastest timing at which actual bus cycles can be resumed after bus control signal
assertion is at the rising edge of the CK where address and data signals are driven. Figure 9.11
shows the bus arbitration timing in master mode.
After BREQ assertion (low level; bus request), the BREQ signal should be negated (high level;
bus release) only after the BACK is asserted (low level; bus acknowledge). If BREQ is negated
before BACK is asserted, BACK may be asserted only for one cycle depending on the BREQ
negation timing, and a bus conflict may occur between the external device and this LSI.
CK
BREQ
BACK
A19 to A0
D7 to D0
CSn
Other bus
control signals
Figure 9.11 Bus Arbitration Timing
Rev. 3.00 Oct. 06, 2008 Page 229 of 1080
REJ09B0230-0300