SH7147 Datasheet, PDF (236/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
9.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 and 1)
CSnWCR specifies various wait cycles for memory accesses. Specify CSnWCR before accessing
the target area. CSnWCR should be modified only after CSnBCR setting is completed.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
WW[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
SW[1:0]
WR[3:0]
WM
-
-
-
-
HW[1:0]
Initial value: 0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R
R
R
R R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 19 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
18 to 16 WW[2:0] 000
R/W Number of Wait Cycles in Write Access
Specify the number of cycles required for write access.
000: The same cycles as WR3 to WR0 settings (read
access wait)
001: 0 cycles
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
15 to 13 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Oct. 06, 2008 Page 212 of 1080
REJ09B0230-0300