SH7147 Datasheet, PDF (179/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 User Break Controller (UBC)
7. User breaks are disabled during UBC module standby mode. Do not read from or write to the
UBC registers during UBC module standby mode; the values are not guaranteed.
8. Do not set a post-execution break at a SLEEP instruction or a branch instruction for which a
SLEEP instruction is placed in the delay slot. In addition, do not set a data access break at a
SLEEP instruction or one or two instructions before a SLEEP instruction.
9. Do not determine the breaks in an external space when the UBC is used in the MCU extension
mode.
Rev. 3.00 Oct. 06, 2008 Page 155 of 1080
REJ09B0230-0300