SH7147 Datasheet, PDF (125/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value R/W Description
3
IRQ11S 0
R/W IRQ1 Sense Select
2
IRQ10S 0
R/W Set the interrupt request detection mode for pin IRQ1.
00: Interrupt request is detected at the low level of pin
IRQ1
01: Interrupt request is detected at the falling edge of
pin IRQ1
10: Interrupt request is detected at the rising edge of
pin IRQ1
11: Interrupt request is detected at both the falling and
rising edges of pin IRQ1
1
IRQ01S 0
R/W IRQ0 Sense Select
0
IRQ00S 0
R/W Set the interrupt request detection mode for pin IRQ0.
00: Interrupt request is detected at the low level of pin
IRQ0
01: Interrupt request is detected at the falling edge of
pin IRQ0
10: Interrupt request is detected at the rising edge of
pin IRQ0
11: Interrupt request is detected at both the falling and
rising edges of pin IRQ0
6.3.3 IRQ Status register (IRQSR)
IRQSR is a 16-bit register that indicates the states of the external interrupt input pins IRQ0 to
IRQ3 and the status of interrupt request.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
- IRQ3L IRQ2L IRQ1L IRQ0L -
-
-
- IRQ3F IRQ2F IRQ1F IRQ0F
Initial value: 1
1
1
1
*
*
*
*
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W
Note: * The initial value is 1 when the level on the corresponding IRQ pin is high, and 0 when the level on the pin is low.
Rev. 3.00 Oct. 06, 2008 Page 101 of 1080
REJ09B0230-0300