SH7147 Datasheet, PDF (246/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
9.5.5 Wait between Access Cycles
As the operating frequency of LSIs becomes higher, the off-operation of the data buffer often
collides with the next data output when the data output from devices with slow access speed is
completed. As a result of these collisions, the reliability of the device is low and malfunctions may
occur. A function that avoids data collisions by inserting wait cycles between continuous access
cycles has been newly added.
The number of wait cycles between access cycles can be set by bits IWW[1:0], IWRWD[1:0],
IWRWS[1:0], IWRRD[1:0], and IWRRS[1:0] in CSnBCR. The conditions for setting the wait
cycles between access cycles (idle cycles) are shown below.
1. Continuous accesses are write-read or write-write
2. Continuous accesses are read-write for different spaces
3. Continuous accesses are read-write for the same space
4. Continuous accesses are read-read for different spaces
5. Continuous accesses are read-read for the same space
Besides the wait cycles between access cycles (idle cycles) described above, idle cycles must be
inserted to reserve the minimum pulse width for a multiplexed pin (WRL), and an interface with
an internal bus.
6. Idle cycle of the external bus for the interface with the internal bus
A. Insert one idle cycle immediately before a write access cycle after an external bus idle
cycle or a read cycle.
B. Insert one idle cycle to transfer the read data to the internal bus when a read cycle of the
external bus terminates.
Insert two to three idle cycles including the idle cycle in A. for the write cycle immediately
after a read cycle.
Tables 9.8 and 9.9 list the minimum number of idle cycles to be inserted. The CSnBCR Idle
Setting column in the tables describes the number of idle cycles to be set for IWW, IWRWD,
IWRWS, IWRRD, and IWRRS.
Rev. 3.00 Oct. 06, 2008 Page 222 of 1080
REJ09B0230-0300