SH7147 Datasheet, PDF (148/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 User Break Controller (UBC)
7.3 Register Descriptions
The user break controller has the following registers. For details on register addresses and register
states during each processing, refer to section 24, List of Registers.
Table 7.2 Register Configuration
Register Name
Abbrevia-
tion
Break address register A
BARA
Break address mask register A BAMRA
Break bus cycle register A
BBRA
Break data register A
BDRA
Break data mask register A BDMRA
Break address register B
BARB
Break address mask register B BAMRB
Break bus cycle register B
BBRB
Break data register B
BDRB
Break data mask register B BDMRB
Break control register
BRCR
Branch source register
BRSR
Branch destination register BRDR
Execution times break register BETR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
Initial Value Address
H'00000000 H'FFFFF300
H'00000000 H'FFFFF304
H'0000
H'FFFFF308
H'00000000 H'FFFFF310
H'00000000 H'FFFFF314
H'00000000 H'FFFFF320
H'00000000 H'FFFFF324
H'0000
H'FFFFF328
H'00000000 H'FFFFF330
H'00000000 H'FFFFF334
H'00000000 H'FFFFF3C0
H'0xxxxxxx H'FFFFF3D0
H'0xxxxxxx H'FFFFF3D4
H'0000
H'FFFFF3DC
Access Size
32
32
16
32
32
32
32
16
32
32
32
32
32
16
Rev. 3.00 Oct. 06, 2008 Page 124 of 1080
REJ09B0230-0300