SH7147 Datasheet, PDF (954/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 23 Advanced User Debugger (AUD)
Bit
Bit Name
31 to 16 ⎯
15, 14 CLK[1:0]
13, 12 ⎯
11
BRE
8
BR
Initial
Value
All 0
00
All 0
0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W AUD Clock Select
Sets CPU clock ratio for AUD internal operation clock.
00: 1/8
01: 1/4
10: 1/2
11: 1/1
Note: Be sure to change the CLK bit while the EN bit
in AUCSR is 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Branch Trace Function
R/W AUD traces branch destination or source address by
settings of these bits.
00: Disables branch trace
01: Enables branch trace. Outputs both destination
and source addresses.
10: Enables branch trace. Outputs source address
only.
11: Enables branch trace. Outputs destination address
only.
The setting of this register is enabled at the output of a
trace executed after setting. The output format after
setting is not reflected in the branch trace data
downloaded in FIFO before setting.
Rev. 3.00 Oct. 06, 2008 Page 930 of 1080
REJ09B0230-0300