SH7147 Datasheet, PDF (17/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

14.4.7 Clock Synchronous Communication Mode ...................................................... 626
14.5 Synchronous Serial Communication Unit Interrupt Sources and DTC............................. 632
14.6 Usage Notes ...................................................................................................................... 633
14.6.1 Module Standby Mode Setting ......................................................................... 633
14.6.2 Access to SSTDR and SSRDR Registers.......................................................... 633
14.6.3 Continuous Transmission/Reception in Synchronous
Serial Communication Slave Mode .................................................................. 633
Section 15 A/D Converter (ADC)......................................................................635
15.1 Features............................................................................................................................. 635
15.2 Input/Output Pins.............................................................................................................. 637
15.3 Register Descriptions ........................................................................................................ 638
15.3.1 A/D Control Registers_0 and _1 (ADCR_0 and ADCR_1).............................. 639
15.3.2 A/D Status Registers_0 and _1 (ADSR_0 and ADSR_1)................................. 642
15.3.3 A/D Start Trigger Select Registers_0 and _1
(ADSTRGR_0 and ADSTRGR_1) ................................................................... 643
15.3.4 A/D Analog Input Channel Select Registers_0 and _1
(ADANSR_0 and ADANSR_1) ....................................................................... 645
15.3.5 A/D Data Registers 0 to 15 (ADDR0 to ADDR15) .......................................... 646
15.3.6 CPU Interface ................................................................................................... 647
15.4 Operation .......................................................................................................................... 648
15.4.1 Single-Cycle Scan Mode................................................................................... 648
15.4.2 Continuous Scan Mode ..................................................................................... 650
15.4.3 Input Sampling and A/D Conversion Time....................................................... 652
15.4.4 A/D Converter Activation by MTU2 and MTU2S ........................................... 654
15.4.5 External Trigger Input Timing.......................................................................... 655
15.4.6 Example of ADDR Auto-Clear Function.......................................................... 655
15.5 Interrupt Sources and DTC Transfer Requests ................................................................. 657
15.6 Definitions of A/D Conversion Accuracy......................................................................... 658
15.7 Usage Notes ...................................................................................................................... 660
15.7.1 Analog Input Voltage Range............................................................................. 660
15.7.2 Relationship between AVcc, AVss and Vcc, Vss ............................................. 660
15.7.3 Range of AV_refh and AV_refl Pin Settings.............................................................. 660
15.7.4 Notes on Board Design ..................................................................................... 660
15.7.5 Notes on Noise Countermeasures ..................................................................... 660
15.7.6 Notes on Register Setting.................................................................................. 661
Section 16 Compare Match Timer (CMT).........................................................663
16.1 Features............................................................................................................................. 663
Rev. 3.00 Oct. 06, 2008 Page xvii of xxiv
REJ09B0230-0300