SH7147 Datasheet, PDF (677/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 15 A/D Converter (ADC)
Table 15.5 Correspondence between Analog Input Channels and Groups being Allowed
Simultaneous Sampling
A/D_0 Converter
Analog Input
Channels
Group
AN0
GrA
AN1
AN2
AN3
⎯
AN4
⎯
AN5
⎯
AN6
⎯
AN7
⎯
A/D_1 Converter
Analog Input
Channels
Group
AN8
GrB
AN9
AN10
AN11
⎯
AN12
⎯
AN13
⎯
AN14
⎯
AN15
⎯
Table 15.6 A/D Conversion Time
Number of Required States
Item
Symbol Min.
Typ.
Max.
A/D conversion start delay time
t_D
11*¹
⎯
15*²
Analog input sampling time of dedicated t
⎯
30
⎯
SPLSH
sample-and-hold circuit for GrA and GrB
Offset canceling processing time
t_OFC
⎯
50
Analog input sampling time of sample- t_SPL
⎯
20
and-hold circuit common to all channels
A/D conversion time
t_CONV
50n + 95*³ ⎯
Notes: 1. A/D converter activation by the MTU2 or MTU2S trigger signal.
2. A/D converter activation by an external trigger signal.
3. n: number of A/D conversion channels (n = 1 to 8)
⎯
⎯
50n + 99*³
Rev. 3.00 Oct. 06, 2008 Page 653 of 1080
REJ09B0230-0300