SH7147 Datasheet, PDF (9/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

5.5.2 Trap Instructions ................................................................................................. 87
5.5.3 Illegal Slot Instructions ....................................................................................... 88
5.5.4 General Illegal Instructions................................................................................. 88
5.6 Cases when Exceptions Are Accepted................................................................................ 89
5.7 Stack States after Exception Handling Ends....................................................................... 90
5.8 Usage Notes ........................................................................................................................ 92
5.8.1 Value of Stack Pointer (SP) ................................................................................ 92
5.8.2 Value of Vector Base Register (VBR) ................................................................ 92
5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling ...... 92
5.8.4 Notes on Slot Illegal Instruction Exception Handling......................................... 93
Section 6 Interrupt Controller (INTC) .................................................................95
6.1 Features............................................................................................................................... 95
6.2 Input/Output Pins................................................................................................................ 97
6.3 Register Descriptions .......................................................................................................... 98
6.3.1 Interrupt Control Register 0 (ICR0).................................................................... 99
6.3.2 IRQ Control Register (IRQCR) ........................................................................ 100
6.3.3 IRQ Status register (IRQSR)............................................................................. 101
6.3.4 Interrupt Priority Registers A, D to F, and H to M
(IPRA, IPRD to IPRF, and IPRH to IPRM)...................................................... 104
6.4 Interrupt Sources............................................................................................................... 107
6.4.1 External Interrupts ............................................................................................ 107
6.4.2 On-Chip Peripheral Module Interrupts ............................................................. 108
6.4.3 User Break Interrupt ......................................................................................... 108
6.5 Interrupt Exception Handling Vector Table...................................................................... 109
6.6 Interrupt Operation ........................................................................................................... 113
6.6.1 Interrupt Sequence ............................................................................................ 113
6.6.2 Stack after Interrupt Exception Handling ......................................................... 116
6.7 Interrupt Response Time................................................................................................... 116
6.8 Data Transfer with Interrupt Request Signals ................................................................... 118
6.8.1 Handling Interrupt Request Signals as Sources for DTC Activation and
CPU Interrupts .................................................................................................. 119
6.8.2 Handling Interrupt Request Signals as Sources for DTC Activation, but Not
CPU Interrupts .................................................................................................. 119
6.8.3 Handling Interrupt Request Signals as Sources for CPU Interrupts, but Not
DTC Activation................................................................................................. 120
6.9 Usage Note........................................................................................................................ 120
Rev. 3.00 Oct. 06, 2008 Page ix of xxiv
REJ09B0230-0300