SH7147 Datasheet, PDF (626/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 14 Synchronous Serial Communication Unit
14.3.4 SS Enable Register (SSER)
SSER performs transfer/receive control of synchronous serial communication and setting of
interrupt enable.
Bit: 7
6
5
TE RE
-
Initial value: 0
0
0
R/W: R/W R/W R
4
3
2
1
0
- TEIE TIE RIE CEIE
0
0
0
0
0
R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
7
TE
0
R/W
6
RE
0
R/W
5, 4 ⎯
All 0
R
3
TEIE
0
R/W
2
TIE
0
R/W
1
RIE
0
R/W
0
CEIE
0
R/W
Description
Transmit Enable
When this bit is set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit End Interrupt Enable
When this bit is set to 1, a SSTEI interrupt request is
enabled.
Transmit Interrupt Enable
When this bit is set to 1, a SSTXI interrupt request is
enabled.
Receive Interrupt Enable
When this bit is set to 1, an SSRXI interrupt request
and an SSOEI interrupt request are enabled.
Conflict Error Interrupt Enable
When this bit is set to 1, a SSCEI interrupt request is
enabled.
Rev. 3.00 Oct. 06, 2008 Page 602 of 1080
REJ09B0230-0300