SH7147 Datasheet, PDF (14/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

10.7.3 Caution on Period Setting ................................................................................. 441
10.7.4 Contention between TCNT Write and Clear Operations.................................. 441
10.7.5 Contention between TCNT Write and Increment Operations........................... 442
10.7.6 Contention between TGR Write and Compare Match ...................................... 443
10.7.7 Contention between Buffer Register Write and Compare Match ..................... 444
10.7.8 Contention between Buffer Register Write and TCNT Clear ........................... 445
10.7.9 Contention between TGR Read and Input Capture........................................... 446
10.7.10 Contention between TGR Write and Input Capture.......................................... 447
10.7.11 Contention between Buffer Register Write and Input Capture ......................... 448
10.7.12 TCNT_2 Write and Overflow/Underflow Contention in Cascade
Connection........................................................................................................ 448
10.7.13 Counter Value during Complementary PWM Mode Stop ................................ 450
10.7.14 Buffer Operation Setting in Complementary PWM Mode ............................... 450
10.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .............. 451
10.7.16 Overflow Flags in Reset Synchronous PWM Mode ......................................... 452
10.7.17 Contention between Overflow/Underflow and Counter Clearing..................... 453
10.7.18 Contention between TCNT Write and Overflow/Underflow............................ 454
10.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to
Reset-Synchronized PWM Mode...................................................................... 454
10.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized
PWM Mode ...................................................................................................... 455
10.7.21 Interrupts in Module Standby Mode ................................................................. 455
10.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection........ 455
10.7.23 Buffer Register Flag Bits in Complementary PWM Mode............................... 455
10.8 MTU2 Output Pin Initialization........................................................................................ 456
10.8.1 Operating Modes............................................................................................... 456
10.8.2 Reset Start Operation ........................................................................................ 456
10.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc............... 457
10.8.4 Overview of Initialization Procedures and Mode Transitions in Case of
Error during Operation, etc. .............................................................................. 458
Section 11 Port Output Enable (POE) ...............................................................489
11.1 Features............................................................................................................................. 489
11.2 Input/Output Pins.............................................................................................................. 490
11.3 Register Descriptions........................................................................................................ 492
11.3.1 Input Level Control/Status Register 1 (ICSR1) ................................................ 493
11.3.2 Output Level Control/Status Register 1 (OCSR1) ............................................ 496
11.3.3 Input Level Control/Status Register 2 (ICSR2) ................................................ 498
11.3.4 Output Level Control/Status Register 2 (OCSR2) ............................................ 501
11.3.5 Input Level Control/Status Register 3 (ICSR3) ................................................ 503
Rev. 3.00 Oct. 06, 2008 Page xiv of xxiv
REJ09B0230-0300