SH7147 Datasheet, PDF (772/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 18 Pin Function Controller (PFC)
18.1.2 Port A Control Registers L1 to L4 (PACRL1 to PACRL4)
PACRL1 to PACRL4 are 16-bit readable/writable registers that are used to select the functions of
the multiplexed pins on port A.
• Port A Control Register L4 (PACRL4)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
PA15 PA15 PA15
MD2 MD1 MD0
-
PA14 PA14 PA14
MD2 MD1 MD0
-
PA13 PA13 PA13
MD2 MD1 MD0
-
PA12 PA12 PA12
MD2 MD1 MD0
Initial value: 0
0
0 0*¹ 0 0*² 0
0
0 0*² 0
0
0 0*² 0
0
R/W: R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W
Notes: 1. The initial value is 1 in the on-chip ROM enabled/disabled external-extension mode.
2. The initial value is 1 in the on-chip ROM disabled external-extension mode.
Initial
Bit
Bit Name Value R/W Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14
PA15MD2 0
R/W PA15 Mode
13
PA15MD1 0
R/W Select the function of the PA15/CK/TXD1/SSO pin.
12
PA15MD0 0*¹
R/W 000: PA15 I/O (port)
001: CK output (CPG)*³
101: SSO I/O (synchronous serial communication unit)
110: TXD1 output (SCI)
Other than above: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10
PA14MD2 0*²
R/W PA14 Mode
9
PA14MD1 0
R/W Select the function of the PA14/A10/RXD1/SSI pin.
8
PA14MD0 0
R/W 000: PA14 I/O (port)
100: A10 output (BSC)*³
101: SSI I/O (synchronous serial communication unit)
110: RXD1 input (SCI)
Other than above: Setting prohibited
Rev. 3.00 Oct. 06, 2008 Page 748 of 1080
REJ09B0230-0300