SH7147 Datasheet, PDF (249/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
• When activation request is generated in the order of DTC and AUD during external space access from CPU
Transfer is started for the request that is generated first
Internal bus
External space access from CPU
DTC
AUD
AUD activation request
DTC activation request
• When activation request is generated in the order of AUD and DTC during external space access from CPU
Transfer is started for the request that is generated first
Internal bus
External space access from CPU
AUD
DTC
AUD activation request
DTC activation request
• When activation request is generated for AUD and DTC at the same time during external space access from CPU
Transfer is started in accordance with the bus priority (AUD>DTC)
Internal bus
External space access from CPU
AUD
DTC
AUD activation request
Priority determination
DTC activation request
[Reference] When activation request is generated in the order of DTC and AUD during access to an on-chip peripheral module by CPU
Transfer is started in accordance with the bus priority (AUD>DTC)
Internal bus
Access to on-chip peripheral module from CPU
AUD
DTC
AUD activation request
DTC activation request
Priority determination
Figure 9.9 Bus Arbitration when DTC and AUD Compete during External Space Access
from CPU
Rev. 3.00 Oct. 06, 2008 Page 225 of 1080
REJ09B0230-0300