SH7147 Datasheet, PDF (32/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 1 Overview
1.2 Block Diagram
SH2
CPU
UBC
AUD
L bus (Iφ)
ROM
RAM
Internal bus
controller
I bus (Bφ)
BSC
Peripheral bus
controller
DTC
External bus
Peripheral bus (Pφ)
I/O
port
(PFC)
SCI
CMT
INTC
Power- WDT
CPG MTU2 MTU2S
POE
Synchro-
nous
ADC
RCAN-ET
down
serial
mode
control
communi-
cation
unit
[Legend]
ROM:
RAM:
UBC:
AUD:
INTC:
CPG:
WDT:
CPU:
BSC:
On-chip ROM
On-chip RAM
User break controller
Advanced user debugger
Interrupt controller
Clock pulse generator
Watchdog timer
Central processing unit
Bus state controller
DTC:
Data transfer controller
PFC:
Pin function controller
MTU2: Multi-function timer pulse unit 2
MTU2S: Multi-function timer pulse unit 2 (subset)
POE:
Port output enable
SCI:
Serial communication interface
CMT:
Compare match timer
ADC:
A/D converter
RCAN-ET: Controller area network
Figure 1.1 Block Diagram
Rev. 3.00 Oct. 06, 2008 Page 8 of 1080
REJ09B0230-0300