SH7147 Datasheet, PDF (633/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 14 Synchronous Serial Communication Unit
14.3.9 SS Shift Register (SSTRSR)
SSTRSR is a shift register that transmits and receives serial data.
When data is transferred from SSTDR to SSTRSR, bit 0 of transmit data is bit 0 in the SSTDR
contents (MLS = 0: LSB first communication) and is bit 7 in the SSTDR contents (MLS = 1: MSB
first communication). The synchronous serial communication unit transfers data from the LSB (bit
0) in SSTRSR to the SSO pin to perform serial data transmission.
In reception, the synchronous serial communication unit sets serial data that has been input via the
SSI pin in SSTRSR from the LSB (bit 0). When 1-byte data has been received, the SSTRSR
contents are automatically transferred to SSRDR. SSTRSR cannot be directly accessed by the
CPU.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: -
-
-
-
-
-
-
-
Rev. 3.00 Oct. 06, 2008 Page 609 of 1080
REJ09B0230-0300