SH7147 Datasheet, PDF (317/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) and Multi-Function Timer Pulse Unit 2S (MTU2S)
Initial
Bit
Bit Name Value R/W Description
1
CMFV5
0
R/(W)*¹ Compare Match/Input Capture Flag V5
Status flag that indicates the occurrence of TGRV_5 input
capture or compare match.
[Setting conditions]
• When TCNTV_5 = TGRV_5 and TGRV_5 is
functioning as output compare register
• When TCNTV_5 value is transferred to TGRV_5 by
input capture signal and TGRV_5 is functioning as
input capture register
• When TCNTV_5 value is transferred to TGRV_5 and
TGRV_5 is functioning as a register for measuring the
pulse width of the external input signal.*²
[Clearing conditions]
• When DTC is activated by a TGIV_5 interrupt and the
DISEL bit of MRB in DTC is 0
• When 0 is written to CMFV5 after reading CMFV5 = 1
0
CMFW5
0
R/(W)*¹ Compare Match/Input Capture Flag W5
Status flag that indicates the occurrence of TGRW_5 input
capture or compare match.
[Setting conditions]
• When TCNTW_5 = TGRW_5 and TGRW_5 is
functioning as output compare register
• When TCNTW_5 value is transferred to TGRW_5 by
input capture signal and TGRW_5 is functioning as
input capture register
• When TCNTW_5 value is transferred to TGRW_5 and
TGRW_5 is functioning as a register for measuring the
pulse width of the external input signal. *²
[Clearing conditions]
• When DTC is activated by a TGIW_5 interrupt and the
DISEL bit of MRB in DTC is 0
• When 0 is written to CMFW5 after reading CMFW5 = 1
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. The transfer timing is specified by the IOC bit in timer I/O control register U_5/V_5/W_5
(TIORU_5, TIORV_5, TIORW_5).
Rev. 3.00 Oct. 06, 2008 Page 293 of 1080
REJ09B0230-0300