SH7147 Datasheet, PDF (681/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 15 A/D Converter (ADC)
15.5 Interrupt Sources and DTC Transfer Requests
The A/D converter generates A/D conversion end interrupts (ADI_3 and ADI_4). An ADI_3
interrupt generation is enabled when the ADIE bit in ADCR_0 is set to 1. An ADI_4 interrupt
generation is enabled when the ADIE bit in ADCR_1 is set to 1. On the other hand, an ADI_3
interrupt generation is disabled when the ADIE bit in ADCR_0 is cleared to 0, and an ADI_4
interrupt generation is disabled when the ADIE bit in ADCR_1 is cleared to 0. The data transfer
controller (DTC) can be activated by the DTC setting when an ADI_3 or ADI_4 interrupt is
generated. When the DTC is activated by an ADI_3 or an ADI_4 interrupt, the ADF bit in
ADSR_0 and ADSR_1 is automatically cleared.
Rev. 3.00 Oct. 06, 2008 Page 657 of 1080
REJ09B0230-0300