SH7147 Datasheet, PDF (724/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 Controller Area Network (RCAN-ET)
(4) Interrupt Request Register (IRR)
The interrupt register (IRR) is a 16-bit read/write-clearable register containing status flags for the
various interrupt sources.
• IRR (Address = H'008)
Bit: 15
-
Initial value: 0
R/W: R
14 13 12 11
- IRR13 IRR12 -
0
0
0
0
R R/W R/W R
10 9
8
7
6
5
4
3
2
1
0
- IRR9 IRR8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0
0
0
0
0
0
0
0
0
0
0
1
R
R
R R/W R/W R/W R/W R/W R
R R/W
Bits 15 to 14: Reserved.
Bit 13 - Message Error Interrupt (IRR13): this interrupt indicates that:
• A message error has occurred when in test mode.
• Note: If a Message Overload condition occurs when in Test Mode, then this bit will not be set.
When not in test mode this interrupt is inactive.
Bit 13: IRR13
0
1
Description
message error has not occurred in test mode (Initial value)
[Clearing condition] Writing 1
[Setting condition] message error has occurred in test mode
Bit 12 – Bus activity while in sleep mode (IRR12): IRR12 indicates that a CAN bus activity is
present. While the RCAN-ET is in sleep mode and a dominant bit is detected on the CAN bus, this
bit is set. This interrupt is cleared by writing a '1' to this bit position. Writing a '0' has no effect. If
auto wakeup is not used and this interrupt is not requested it needs to be disabled by the related
interrupt mask register. If auto wake up is not used and this interrupt is requested it should be
cleared only after recovering from sleep mode. This is to avoid that a new falling edge of the
reception line causes the interrupt to get set again.
Please note that the setting time of this interrupt is different from the clearing time of GSR4.
Bit 12: IRR12
0
1
Description
bus idle state (Initial value)
[Clearing condition] Writing 1
[Setting condition] dominant bit level detection on the Rx line while in sleep
mode
Rev. 3.00 Oct. 06, 2008 Page 700 of 1080
REJ09B0230-0300