SH7147 Datasheet, PDF (91/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 4 Clock Pulse Generator (CPG)
Initial
Bit
Bit Name Value R/W Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12 IFC[2:0] 011
R/W Internal Clock (Iφ) Frequency Division Ratio
Specify the division ratio of the internal clock (Iφ)
frequency with respect to the output frequency of PLL
circuit. If a prohibited value is specified, subsequent
operation is not guaranteed.
000: ×1
001: ×1/2
010: ×1/3
011: ×1/4
100: ×1/8
Other than above: Setting prohibited
11 to 9 BFC[2:0] 011
R/W Bus Clock (Bφ) Frequency Division Ratio
Specify the division ratio of the bus clock (Bφ)
frequency with respect to the output frequency of PLL
circuit. If a prohibited value is specified, subsequent
operation is not guaranteed.
000: ×1
001: ×1/2
010: ×1/3
011: ×1/4
100: ×1/8
Other than above: Setting prohibited
Rev. 3.00 Oct. 06, 2008 Page 67 of 1080
REJ09B0230-0300