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SH7147 Datasheet, PDF (65/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family | |||
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Section 2 CPU
2.5.4 Logic Operation Instructions
Table 2.13 Logic Operation Instructions
Instruction
Operation
AND Rm,Rn
Rn & Rm â Rn
AND #imm,R0
R0 & imm â R0
AND.B #imm,@(R0,GBR) (R0 + GBR) & imm â
(R0 + GBR)
NOT Rm,Rn
~Rm â Rn
OR Rm,Rn
Rn | Rm â Rn
OR #imm,R0
R0 | imm â R0
OR.B #imm,@(R0,GBR) (R0 + GBR) | imm â
(R0 + GBR)
TAS.B @Rn
If (Rn) is 0, 1 â T;
1 â MSB of (Rn)
TST Rm,Rn
Rn & Rm; if the result
is 0, 1 â T
TST #imm,R0
R0 & imm; if the result
is 0, 1 â T
TST.B #imm,@(R0,GBR) (R0 + GBR) & imm;
if the result is 0, 1 â T
XOR Rm,Rn
Rn ^ Rm â Rn
XOR #imm,R0
R0 ^ imm â R0
XOR.B #imm,@(R0,GBR) (R0 + GBR) ^ imm â
(R0 + GBR)
Code
Execution
Cycles
0010nnnnmmmm1001 1
11001001iiiiiiii 1
11001101iiiiiiii 3
T Bit
â¯
â¯
â¯
0110nnnnmmmm0111 1
â¯
0010nnnnmmmm1011 1
â¯
11001011iiiiiiii 1
â¯
11001111iiiiiiii 3
â¯
0100nnnn00011011 4
Test result
0010nnnnmmmm1000 1
Test result
11001000iiiiiiii 1
Test result
11001100iiiiiiii 3
Test result
0010nnnnmmmm1010 1
â¯
11001010iiiiiiii 1
â¯
11001110iiiiiiii 3
â¯
Rev. 3.00 Oct. 06, 2008 Page 41 of 1080
REJ09B0230-0300
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