SH7147 Datasheet, PDF (193/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Data Transfer Controller (DTC)
8.3 Activation Sources
The DTC is activated by an interrupt request. The interrupt source is selected by DTCER. A DTC
activation source can be selected by setting the corresponding bit in DTCER; the CPU interrupt
source can be selected by clearing the corresponding bit in DTCER. At the end of a data transfer
(or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or
corresponding DTCER bit is cleared.
8.4 Location of Transfer Information and DTC Vector Table
Locate the transfer information in the data area. The start address of transfer information should be
located at the address that is a multiple of four (4n). Otherwise, the lower two bits are ignored
during access ([1:0] = B'00.) Transfer information located in the data area is shown in figure 8.2.
The DTC reads the start address of transfer information from the vector table according to the
activation source, and then reads the transfer information from the start address. Figure 8.3 shows
correspondences between the DTC vector address and transfer information.
Transfer information
Lower addresses
Start
address 0 1 2 3
MRA MRB
Reserved
(0 write)
SAR
Chain
transfer
DAR
CRA
CRB
MRA MRB
Reserved
(0 write)
SAR
DAR
CRA
CRB
Transfer
information
for one transfer
(4 longwords)
Transfer
information
for the 2nd
transfer
in chain transfer
(4 longwords)
4 bytes
Figure 8.2 Transfer Information on Data Area
Rev. 3.00 Oct. 06, 2008 Page 169 of 1080
REJ09B0230-0300